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Altera_Forum
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14 years ago

TSE MAC and marvell phy 88e1111 troubleshooting

Hi ,all

I am using development tools:Quartus II 10.1,Nios IDE 10.1.Hardware :Arria II GX,

EP2AGX260FF35I5N.

I am using TSE MAC and the tools described above,and a custom board with the devices described above.The FPGA design of the custom board is largely based on Cyclone II ep3c120 development kit (with revisions to the type of memory used and input frequency (20 Mhz instead of 50 Mhz ,and working frequency of the SOPC system.I am using MARVELL PHY 88E1111,the same as on evaluation board (s) ).Software running on Nios II processor is the same as the on running on evaluation board and it is lwip-based TCP/IP stack.(http://www.alteraforum.com/forum/showthread.php?t=23787).on the evaluation board it works correctly.

On my custom board,on the other hand,it does not function properly.It doesn't reply to ping requests correctly.After deep inquiring of the issue,i was able to isolate the problem:The RX path works perfectly ,and the ping is received correctly ,and the SW tries to reply to the ping.But I am not able to see any ARP response from the board (the MAC) on my wireshark sniffer.After thorough debugging I was able to see that the SW does reply to the ping,and i am able to see data on ethernet TXD lines and TX_EN line rise every ping.At first I suspected PHY error and after comparing PHY registers at points of initialization,after receiving ping request and after sending ping reply I was able to see that PHY raises FIFO over/underflow error.After comparing the TX signals between my board and evaluation board (GTX_CLK and ENET_TXD0) I can see that both boards return the same data pattern,but my custom board returns data at TXD0 ,which somehow is wider by a clock pulse (about 100 ns larger ,at the speed of 100 Mbps,25 Mhz CLK).This could be the cause for the error.Also, I would like to point out that the PHY is overheating (though the temperature is in valid range ,comparing to evaluation board PHY ,which is not ).So I would like to know what is the source of the error and how to solve it .Thank You.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I had similar problems when RX worked as it should be, but TX not at all. Everything was solved by constraining a design properly. Firstly add all available clocks (incl. 125MHz, 25MHz, 2.5MHz), etc.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    First of all,thank you for your response.

    I hear this advice of constraining the design properly all the time,but I still have no idea what does that mean,practically.

    Add which clocks,to which constraint file?

    If there are some timings to be added,how do I calculate them ?

    Thank You.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Learn how to constrain Your design. Start by using TimeQuest timing analyzer - it will show all the failing timing paths and all timing problems. There is a good tutorial pdf on alterawiki.com + search for timing literature at altera.com.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I have noticed bizzarre phenomenon in using sdc files-In evaluation board I do see timing analysis critical warnings,with failures and everything (But it works perfectly ),but on my custom board,which does not work correctly,I don't see any warnings and it works fine according to Time Quest analyzer.What i do see is some other ,non-critical ,warnings,such as :

    -- Info: set_clock_uncertainty -rise_from [get_clocks {this_cycloneIII_3c120_dev_niosII_standard_SOPC|the_pll|sd1|pll7|clk[0]}] -fall_to [get_clocks {this_cycloneIII_3c120_dev_niosII_standard_SOPC|the_pll|sd1|pll7|clk[0]}] -setup 0.020

    -- Warning: Clock: this_cycloneIII_3c120_dev_niosII_standard_SOPC|the_pll|sd1|pll7|clk[0] with master clock period: 20.000 found on PLL node: this_cycloneIII_3c120_dev_niosII_standard_SOPC|the_pll|sd1|pll7|clk[0] does not match the master clock period requirement: 50.000

    -- Warning: Ignored create_clock at a2gx260_fpga_bup.sdc(42): Incorrect assignment for clock. Source node: altera_reserved_tck already has a clock(s) assigned to it. Use the -add option to assign multiple clocks to this node. Clock was not created or updated.

    Info: create_clock -period 100 -name tck [get_ports {altera_reserved_tck}]
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Got the board partially working.It turned out that incorrect clock was supplied to GTX_CLK .

    The problem i am running into right now is as follows:

    - I am able to ping the board about 10-15 minutes past initialization.At that period of time,I am able to ping most of the packets correctly.The ping requests which are timed out are ICMP replies which are corrupt (failed checksum) ( I am able to see that in Wireshark).

    -After that time is passed (10-15 minutes),I am receiving ping requests ,but the board does not reply (Probable cause is that the frame ,which includes ethernet,ip and icmp , that is received is corrupted,as I can see on debug that icmp_input () callback function is not entered).

    What could be the problem and how can It be solved?

    Thank You.