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Altera_Forum
Honored Contributor
14 years agoI have noticed bizzarre phenomenon in using sdc files-In evaluation board I do see timing analysis critical warnings,with failures and everything (But it works perfectly ),but on my custom board,which does not work correctly,I don't see any warnings and it works fine according to Time Quest analyzer.What i do see is some other ,non-critical ,warnings,such as :
-- Info: set_clock_uncertainty -rise_from [get_clocks {this_cycloneIII_3c120_dev_niosII_standard_SOPC|the_pll|sd1|pll7|clk[0]}] -fall_to [get_clocks {this_cycloneIII_3c120_dev_niosII_standard_SOPC|the_pll|sd1|pll7|clk[0]}] -setup 0.020 -- Warning: Clock: this_cycloneIII_3c120_dev_niosII_standard_SOPC|the_pll|sd1|pll7|clk[0] with master clock period: 20.000 found on PLL node: this_cycloneIII_3c120_dev_niosII_standard_SOPC|the_pll|sd1|pll7|clk[0] does not match the master clock period requirement: 50.000 -- Warning: Ignored create_clock at a2gx260_fpga_bup.sdc(42): Incorrect assignment for clock. Source node: altera_reserved_tck already has a clock(s) assigned to it. Use the -add option to assign multiple clocks to this node. Clock was not created or updated. Info: create_clock -period 100 -name tck [get_ports {altera_reserved_tck}]