Trouble with creating multiprocessor Nios II system with shared memory

Question

Hello,

I have created a multiprocessor Nios II system with two cpus sharing on-chip memory to print to the console (JTAG UART). I used the Altera "Creating Multiprocessor Nios II Systems Tutorial" for reference. I also used the example application hello_world_multi.c that is used in this tutorial. I got it off the Altera website.

It worked fine for a system with two CPUs, but it did not work when I tried it for three or four cpus. According to the tutorial, this application is expected to work for three (or more) CPUs. But when I tried that, only two of the CPUs print to the console while the other one/two are starved. It appears like the first two CPUs who get the mutex, get it always and the other(s) is/are starved. Since this application is expected to work for three CPUs, I don't see why this should happen.

I am using the Altera DE2 board, Quartus II 8.0 and Nios II IDE 8.0. My SOPC system has three CPUs, a mutex core and a shared memory component. I would appreciate any help/insight with this.

Thanks.

altera_forum · Answer

Are all your Cpus trying to lock the mutex at the same time? Arbitration between different Avalon masters isn't always fair, and it could result in giving access to the same CPUs.

You could try and acquire the mutex through the altera_avalon_mutex_trylock() and wait a random number of cycles before trying again if it fails.

altera_forum · Answer

I'm not familiar enough with the example design but my first impression is the same as Daixiwen's. It sounds like the first two cpu's are beating out the other two when aquiring the mutex. If you want some mechanism to ensure everyone gets a fair shot at it, you're going to have to add it.

If you want to verify that the other processors can indeed get the mutex, you can run all processor's in the debugger, then pause the first two and see if the other processors are able to get the mutex.

Jake

altera_forum · Answer

Goto Quartus meniu "Assignements" find "Device". After that find Analysis & Synthesis Settings and uncheck: Power-Up Don't Care.

If this will not help. Try to build some counter that holds reset for example one second. Maybe there is a problem that CPU3 is gets not all software from EPCS and try to run when it incomplete. So reset hold may help to solve this problem.

altera_forum · Answer

Thanks for your replies, everyone. I went to SOPC builder 'View' menu --> 'Show Arbitration' and increased the Arbitration share for the starved CPU. That is working for now. But it appears like I need to acquire more knowledge about arbitration on the Avalon Bus.

Are the 'Avalon Bus' and 'Avalon Interconnect for Avalon MM components' essentially the same? I did not find any specification manual for the 'Avalon Bus' on the Altera website. The SOPC builder 'Help' also talks about 'Avalon Interconnect' rather than the 'Avalon bus'.

Thanks.

altera_forum · Answer

Avalon Bus refers to basically the signals available to Avalon MM slaves and masters and how they function. Avalon Interconnect Fabric refers to the overall bus interconnect system (how masters and slaves are wired together, how arbitration is handled, how addressing is handled, etc.)

Jake

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Trouble with creating multiprocessor Nios II system with shared memory

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