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Altera_Forum
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12 years ago

Triple Speed Ethernet and transceiver blocks

We have a Nios2/s processor running a triple speed ethernet (TSE) with a scatter gather DMA. Working off the of the triple speed ethernet example from altera for our board (DE4 Stratix IV board), the...
Altera_Forum's avatar
Altera_Forum
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11 years ago

my bad, I thought it was a regular Stratix 4.

In that case, can you check that the target for the TSE core is indeed the correct FPGA family. I just created a test project with a Stratix 4 GX and I had no problem checking the "use transceiver block", as long as the TSE type that I selected was "10/100/1000Mb Etheret MAC with 1000BASE-X/SGMII PCS"