Tri-state bus with HDL files

Hi,

Thanks for the link, but unless I'm missing something that concerns adding a normal peripheral to the internal avalon bus, not a peripheral to the tri-state bus.

I shall attempt to clarify my situation a little more! In my design, there are a number of peripherals (e.g. LCD controller) that hang directly off the internal avalon bus and connect to some dedicated pins which work correctly and with no problems. Also on our board, there is an external bus that has shared data, address, read and write signals with separate chipselects for the SRAM / FLASH / USB interface chip etc.

What I need to do is add peripherals that use these shared signals but with separate chipselects. It appears from the documentation that this is done by using the bidirectional 'data' signal (along with read and write) rather than separate 'readdata' and 'writedata' signals.

This works correctly if I add an interface to user logic, don't import any HDL files and define the ports manually. However, I need to be able to have more control over a couple of the external devices and generate some extra signals during reads / writes. If I import a HDL file (in my case verilog) during the process of adding the interface to user logic then it appears that the data bus is not shared for these interfaces and chip select signals are not generated!

Hopefully this makes things a little clearer.

Alistair