transfer data problem

Hi, I use QuartusII 4.0, Nios 3.1 and Stratix 1S10.

I design an user logic circuit. There are 3 registers in it, and each of them has its own address.

In software, I write data to these register sequentially, like

*p = 10.0; // p is the address of the first register, (p+1) is the address of the second register

*(p+1) = 15.0;

.

.

.

Then I use modelsim to observe the waveform, and I find there are 11 clock between the two transfer.

That means after the first transfer for the first register, and wait 11 clk, then the second transfer starts.

Why there are so many clock cycles between these two transfer ?

Thanks a lot. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/ohmy.gif