Timing Requirements

Hi all, I've a StratixII Development Kit (no RoHS). I've projected my custom niosII with a PLL to improve the clock frequency speed, but after I've compiled the project, in the "Timing Analyzer" report I found :

Timing Analizer Summary :

Slow Model Recovery: 'NiosII_EPS60_Tesi:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk0' -3.717 ns 1.824 ns 5.541 ns NiosII_EPS60_Tesi:inst|pll:the_pll|count_done NiosII_EPS60_Tesi:inst|NiosII_EPS60_Tesi_reset_pll_c0_domain_synch_module:NiosII_EPS60_Tesi_reset_pll_c0_domain_synch|data_out    CLOCK NiosII_EPS60_Tesi:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk0 2

and in Timing Analyzer -> Slow/Fast Model -> Recovery: 'NiosII_EPS60_Tesi:inst.....

-3.717 ns NiosII_EPS60_Tesi:inst|pll:the_pll|count_done NiosII_EPS60_Tesi:inst|NiosII_EPS60_Tesi_reset_pll_c0_domain_synch_module:NiosII_EPS60_Tesi_reset_pll_c0_domain_synch|data_out    CLOCK NiosII_EPS60_Tesi:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk0 1.824 ns 5.541 ns
-3.717 ns    NiosII_EPS60_Tesi:inst|pll:the_pll|count_done NiosII_EPS60_Tesi:inst|NiosII_EPS60_Tesi_reset_pll_c0_domain_synch_module:NiosII_EPS60_Tesi_reset_pll_c0_domain_synch|data_in_d1 CLOCK NiosII_EPS60_Tesi:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk0 1.824 ns 5.541 ns

Can someone tell me somethig about this warning ? Where can i found some info ?

Sorry for my bad english. Thanks in advice.

Greetings