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Altera_Forum
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11 years ago

Timing delay of reading from second RAM in FPGA.

Hi all, I have a question that has been bothering me for almost a week and hopefully someone could help me out. Here is my plan, there are 2 RAMs in FPGA, one receives data from HPS, call it RAM0,...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Hi fannyfang,

The Cortex-A9 supports out-of-order execution. If you are executing a series of instructions that do not depend on the data from previous instructions, they may execute in an order other than what you have written in your code. You can read more about it in the TRM.

Regards,

Sue