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Altera_Forum
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12 years ago

Tightly Coupled OnChip DMA

Hi, I've got some very strange 'performance behavior' with a tightly coupled on chip memory used as data storage. In order to speed up my design, I've created a tightly coupled on chip memory w...
Altera_Forum's avatar
Altera_Forum
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12 years ago

IIRC the arbiter is likely to have given both master the same priority, and also to avoid switching between equal priority masters unless they release their 'request'. I think you can change the priority by right clicking on the intersection.

The dma controller could easily be doing full bandwidth transfers on both the source and destination avalon slaves.

So if the cpu needs to access one of those slaves it could easily get locked out.