Tightly-coupled interface to custom components

When you use a data cache line size of 4B/line or no cache at all the Nios II core does not have a readdatavalid signal hooked up to the fabric. Without this signal Nios II is not able to perform pipelined reads and as a result you should expect read turn around times to affect the performance. Also if any master that supports pipelined reads (has a readdatavalid signal) has reads that are outstanding it will not be able to begin reading from another slave port until all the previous reads returns. So for example with the Nios II 'f' core you can say read 32 back to back bytes from SDRAM and then read from the PIO core immediately after. The reads from the SDRAM must return before the read from the PIO core is allowed to complete (waitrequest will be asserted by the fabric).