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Altera_Forum
Honored Contributor
16 years agoThis is only template for guidance(haven't checked syntax)
library ieee;
use ieee.std_logic_1164.all;
entity move is
port(
dataa: in std_logic_vector(31 downto 0);
datab: in std_logic_vector(31 downto 0);
result: out std_logic_vector(31 downto 0);
clk: in std_logic;
clk_en :in std_logic;
start: in std_logic;
reset: in std_logic;
done: out std_logic
);
end move;
architecture behave of move is
signal t: std_logic_vector(3 downto 0);
signal a: std_logic_vector(31 downto 0);
signal b: std_logic_vector(31 downto 0);
begin
process(clk,reset)
begin
if(reset = '1')then
a <= (others => '0');
b <= (others => '0');
t <= (others => '0');
done <= '0';
result <= (others => '0');
elsif(clk'event and clk='1')then
if(clk_en = '1')then
if(start = '1')then
a <= dataa;
b <= datab;
t <= "0000";
done <= '0';
result <= (others => '0');
end if;
if(t < "1111")then
a <= a+1;
b <= b+1;
t <= t+1;
done <= '0';
else
done <= '1';
result <= a+b;
end if;
end if;
end if;
end process;
end behave;