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I have a signal to be up-converted inside the FPGA.
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What is the signal bandwidth?
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now my question is how high frequency,roughly, I can get from (LUT or NCO) as a carrier frequency. I tried to make the up conversion in Matlab and just store it at the LUT but I realized that I'm having different frequency from the HSMC output.. so I started to wonder about how high I can get!
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FPGAs can be used to process samples
in parallel, so the frequency of the FPGA does not have to match the frequency of the signal. I have systems that process 1GHz clock rate sampled data; inside the FPGA, the data is processed at 125MHz clock rate, with 8 samples processed every clock. I am currently testing 20GHz clock rate ADCs, where 128 samples are processed every clock at 20GHz/128 = 156.25MHz, or 64 samples are processed at twice that frequency.
In the case of a narrow bandwidth signal that needs to be modulated to higher frequencies, you can use multirate sampling filters.
Cheers,
Dave
Honored Contributor
