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Altera_Forum's avatar
Altera_Forum
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13 years ago

The execution time of software

I am using DE2 device. I have built a SOPC system. Through nios II, I'm trying to create a simple process and send this process to FPGA board. 


       IOWR(PI_Control_BASE,0,0); // Send zero to GPIO of FPGA
       PI_val=PI_control(500); // PI_control is a subsystem
       IOWR(PI_Control_BASE,0,1); // Send one to GPIO of FPGA

The purpose of this action is I want to measure the execution time of PI_control when we use software implement.

When I change the interrupt time of Nios, the execution time of PI_control also change.

Can you have any idea to check the execution time of software?

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    The execution times are reasonably fixed (and determinable) provided that:

    1) there is no contention for Avalon slaves

    2) there are no delays waiting for anything external (eg JTAD UART)

    3) the cache transfers are the same

    4) the branch predictor behaves the same way.

    To get trully determinable execution times you need to use tightly coupled memory for code and (most) data, and to disable the dynamic branch prediction.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Thank you very much.

    In my system, I have only one output was connected to GPIO for get the signal (the execution time - signal = 1 the function are processing, signal =0 the function aren't processing). From that information I found the execution time of my process.

    the procedure of my system below:

    Firstly, Nios II sends zero to FPGA ~~~~> Secondly, Nios II processes the function (which I need to know the execution time) ~~~~> Thirdly, Nios II sends one to FPGA.

    The signal (0 and 1) was sent from Nios to FPGA, I can measure from the GPIO of FPGA board.

    --- Quote Start ---

    The execution times are reasonably fixed (and determinable) provided that:

    1) there is no contention for Avalon slaves

    --- Quote End ---

    Can you tell me more information about this?

    --- Quote Start ---

    2) there are no delays waiting for anything external (eg JTAD UART)

    --- Quote End ---

    In FPGA board I have only one SOPC and one pin connect to 1 GPIO

    --- Quote Start ---

    3) the cache transfers are the same

    --- Quote End ---

    What is the cache transfers. Where can I check it?

    --- Quote Start ---

    4) the branch predictor behaves the same way.

    --- Quote End ---

    What is the branch predictor behaves?

    --- Quote Start ---

    To get trully determinable execution times you need to use tightly coupled memory for code and (most) data, and to disable the dynamic branch prediction.

    --- Quote End ---

    I didn't have any code In FPGA board accept SOPC and one output.