Altera_Forum
Honored Contributor
16 years agoTesting some flash routines
Hello,
I am trying to test some flash routines, really just modified mem_test from Nios apps on a new product board that has no external reset. The board is a working FPGA( CIII) that has actually booted from the EPCS with no Nios What I have tried: 1. My first thought, I thought I was being clever, was to convert my time-limited SOF to a JIC. Then download my Nios system into the EPCS. Since my Nios and test code are basically just a hex file attached to a SOF( using on-chip memory) I thought that I could just open a shell and listen with the nios2-terminal as I powered on the FPGA. This does not work, it may, because I cannot convert the time-limited SOF( I cannot attach the SOF file to the JIC creation). 2. Program SOFw/ hex. This is okay, but I see no Nios messages from the shell with a nios2-terminal? 3. Try debugging from IDE( seems like this is not recommended by Altera anymore, want users to use CLI). I try this after I have loaded SOF w/hex and I get strange message: Warning: trying to use little-endian srec with big-endian hardware Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Pausing target processor: not responding. Resetting and trying again: FAILED Leaving target processor paused Possibilities? 1. Use the System Console, haven't tried yet. Help menu a little cryptic. Not sure how to restart Nios from Console. Maybe this will work? Thanks in advance for any suggestions. Regards