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Altera_Forum's avatar
Altera_Forum
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16 years ago

system verilog simulation support in modelsim

hi all,

Does Altera Modelsim 6.5b supports system verilog simulation?

I am simulating verilog files in which i have included system verilog .sv files using this modelsim version but it was giving error " Error: ecc_conf_model.sv(12): near "class": syntax error, unexpected "IDENTIFIER", expecting "class" ". To solve this i changed extension from .v to .sv so this error removed but when i go for nios to modelsim simulation same problem occurs because of sopc top level simulation .v file.

so what is the solution for this...?

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Yes, Modelsim does simulate system Verilog fine.

    But you need to tell it that the files are "system verilog". To do do go to the settings and change the default verilog file type to "System Verilog".
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Up.

    I know ModelSim works fine with SystemVerilog Files.

    I have lot of .sv

    with Type : SystemVerilog

    with Language Syntax : use SystemVerilog

    This error is everywhere on the web but i have not found any solution till now.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    I believe you have to purchase a license from Mentor that supports SystemVerilog. That being said, I heard that supposedly Modelsim will support synthesizable SystemVerilog without the SystemVerilog license (not entirely sure on this).

    Jake