System ID on FPGA is not match

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originally posted by alexs@Feb 2 2006, 04:06 AM

dear altera developers !

i understand that in this case in system must be

jtag uart and

cpu with debug

and sysid

http://forum.niosforum.com/work2/style_emoticons/<#emo_dir#>/mad.gif

but maybe is it possible somehow to make system where

not present jtag uart , cpu without debug, and no sysid ?

and where for code downloading used custom board like in previous version

version: 1.0 service pack 1, build: 393b

i braked down about new nios2 software download system http://forum.niosforum.com/work2/style_emoticons/<#emo_dir#>/sad.gif

because i make 2 boards based on nios2 (both under serial production) and now i don&#39;t have any poblem and quastion to hardware - it work good

from other side we want to solve software bags which corrected in new vesrion of nios5.1 - we have very big soft projects

but how i understand it is not possible !!!!!!!!!!!!!!! http://forum.niosforum.com/work2/style_emoticons/<#emo_dir#>/mad.gif

i can&#39;t implement hardware without jtag debug and sysid because i don&#39;t have free logic elements for it http://forum.niosforum.com/work2/style_emoticons/<#emo_dir#>/sad.gif

my project are developed on nios2 - and copmatiblity are lost !!!!!!!!!!!!!!!!!!!!!!

need only old flash pogrammer !!!!!!!

help please !

if it possible

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=12506)

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Hi AlexS,

You don&#39;t need the JTAG UART or sysid to use the 5.1 flash programmer. The Flash Programmer Users Guide lists the minimum system requirements need to have your own design program the flash in Table 1-1. A minimum system should have a Flash memory interface(CFI), a tri-state bridge and a Nios processor with a minimum debug level of 1. You are ready have two of the three elements.

I understand that your design does not have the room for the minimum Nios II debug core addition of a few hundred LEs. But there is a solution, since FPGA are re-configurable you can always create a copy of your design that has most peripherals removed except for the minimum system requirments for flash programming (and you keep the same pin out).

Once you create a "new" copy of your "flash program only" design with the nios ii debug level set to 1 , you can compile this in Quartus and load this "flash program only" version of your design before you program the flash.

The only difference in the steps you have to follow after you configure the FPGA, is that you have to use the Flash programmer commandline mode to flash program the chip (the IDE flashprogrammer always checks for a valid sysID (if available) and system timestamp based on what I see in the log outputs). Using the commandline mode you can skip the -sidp (system ID peripheral check) and -timestamp (timestamp check of system) -- see below switch choices highlighted in green.

This should allow you to program your Flash chip and then you can configure the FPGA with your original design.

I hope this helps.

Regards,

-ATJ

BTW: I think one of the useful features of the new 5.1 flash programmer is that (if you have the room on your FPGA chip) this is a simple way to have your Nios II design have a built in Flash program upgrade path when your design is out in the field.

Flash Programmer options:

C:\>nios2-flash-programmer -h

usage: nios2-flash-programmer [-h/--help] [-c/--cable <cable name>]

[-d/--device <device index>] [-i/--instance <instance>]

[-s/--sidp <address>] [-I/--id <id>] [-t/--timestamp <timestamp>]

-b/--base <address> [-e/--epcs]

<action> [-g/--go]

actions can be either:

[--erase-all | --erase <bytes>] [--no-keep-nearby] [--verify] <file>*

--read <filename> [--read-bytes <start>+<size>]

-h/--help Print this message

-Q/--quiet Don&#39;t print anything if everything works

--debug Print debug information

-c/--cable <cable name> Specifies which JTAG cable to use (not needed if

you only have one cable)

-d/--device <device index> Specifies in which device you want to look for the

Nios II debug core (1 = device nearest TDI etc.)

-i/--instance <instance> Specifies the INSTANCE value of the debug core

(not needed if there is exactly one on the chain)

-s/--sidp <address> Base-address of System ID peripheral on target

-I/--id <system-id-value> Unique ID code for target system

-t/--timestamp <time-stamp> Timestamp for target-system (when last generated)

--accept-bad-sysid Continue even if the system ID comparison fails

-b/--base <address> Base address of FLASH/EPCS to operate on

-e/--epcs This operation is on an EPCS flash

-E/--erase <start>+<size> Erase a range of bytes in the flash, or the entire

--erase-all flash before/instead of programming it.

-P/--program Program flash from the input files (the default)

--no-keep-nearby Don&#39;t preserve bytes which need to be erased but

which aren&#39;t specified in the input file

-Y/--verify Verify that contents of flash match input files

<filename>* The names of the file(s) to program or verify

-R/--read <file> Read flash contents into file

-B/--read-bytes <start>+<size> Specify which bytes to read

-g/--go Run processor from reset vector after program.

Input files should be in Motorola S-Record format. Addresses within the files

are interpreted as offsets from the base address of the flash. Output files

written by the tool are in the same format.

The flash programmer supports all CFI flashes which use the AMD programming

algorithm (CFI algorithm 2) or the Intel algorithm (1 or 3).