System ID on FPGA is not match

Dear Altera developers !

I understand that in this case in system must be

JTAG uart and

CPU with debug

and sysid

http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/mad.gif

But maybe is it possible somehow to make system where

not present JTAG uart , CPU without debug, and no sysid ?

And where for code downloading used custom board like in previous version

Version: 1.0 Service Pack 1, Build: 393b

I braked down about new nios2 software download system http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif

because i make 2 boards based on nios2 (both under serial production) and now i don&#39;t have any poblem and quastion to hardware - it work good

From other side we want to solve software bags which corrected in new vesrion of nios5.1 - we have very big soft projects

But how i understand it is not possible !!!!!!!!!!!!!!! http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/mad.gif

I can&#39;t implement hardware without JTAG debug and sysid because i don&#39;t have free logic elements for it http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif

My project are developed on NIOS2 - and copmatiblity are lost !!!!!!!!!!!!!!!!!!!!!!

Need only old flash pogrammer !!!!!!!

HELP please !

if it possible