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Altera_Forum
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21 years ago

Synchronous SRAM - Instruction and Data memory

Hello, Has anyone implemented synchronous sram for Nios instruciton and data store (ie execute out of synch sram)? I'm sure it can be done, but I'm wondering about the performance hit ...
Altera_Forum's avatar
Altera_Forum
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21 years ago

Eric,

Thanks for looking at the part. I think we are in agreement - It may take one or two clocks to retrieve data http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif

Just depends on the capabilities of IUL. I&#39;ve looked at the timing in detail on the logic analyzer many times and the waveforms look just like the picture in the IUL Wizard, but what I don&#39;t know is exactly which clock the LDW was started on. If there is a one clock delay until the address is actually put on the bus and WE_ activates, etc. then we&#39;re at two clocks minimum. (of course this would apply to any memory, not just SSRAM)

Thanks,

Ken