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Altera_Forum
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21 years ago

Synchronous SRAM - Instruction and Data memory

Hello, Has anyone implemented synchronous sram for Nios instruciton and data store (ie execute out of synch sram)? I'm sure it can be done, but I'm wondering about the performance hit ...
Altera_Forum's avatar
Altera_Forum
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21 years ago

PS:

A couple other items I thought about.

Its interesting that all the Altera demo boards use a bank of external asynch SRAM for nios store. You can probably get some extra performance from synch ram, but the million dollar question is -how much?-

Then, if you think about it, the SRAMS that are implemented on chip to the FPGA are most likely all sychronous (may need to read a bit here). So the bus interface must work well with synch rams also.

Most of my apps have had plenty of real time using asych ram at 25Mhz. So, I have not really looked at any benchmarks.

I'll go take a look at whats on the Altera website.

Eric