Synchronous SRAM - Instruction and Data memory

http://www.cypress.com/cfuploads/img/produ...s/cy7c1355b.pdf (http://www.cypress.com/cfuploads/img/products/cy7c1355b.pdf)

page 26 has the read/write timing.

This part does indeed not require the 3 clock latency. You still are on a pipelined access, where the write (or invert for read) gets clocked into the device, and then data is presented or clocked out on the next edge.

The standard asynch nios cycle that I have seen, would want to apply the control signals following an edge, and then get the data on the next edge (ie access to an asynch SRAM).

I have not run thru all the IUL permutations/possibilities, but this is the way I think the standard nios cycle will work (unless there is some sort of synch mode I havent seen).

what is interesting about this mode is that you could run nios 0 wait state (no handshaking to determine latency) with the SRAM running with a phase delayed or perhaps even inverted (180 degree shift) clock. This will take some timing analysis to implement details.

Thanks for the info,

Eric