Synchronous SRAM - Instruction and Data memory

Eric,

They don't. It's the No Bus Latency or Zero Bus Turnaround feature that eliminates that problem when changing addresses or Read/Write direction. The Flowthrough basically makes it Asynchronous on the back side.

So unless someone else knows more, ZBT/FT SSRAM is good stuff. Here is my summary:

Fmax < 100 MHz: Use Asynch SRAM (10ns)

Fmax < 133 MHz: Use ZBT,FT SSRAM (6.5ns)

Fmax > 133 MHz: Use ZBT, pipelined SSRAM (3ns)

SSRAM will additionally perform much better for sequential access if a smart controller that supports Burst mode is used. Then you can get data in or out every 6.5ns (FT) or <3.5ns (pipelined)

Actually, If I read the datasheet correctly, I could read random values every 6.5ns if the controller would present the next address to the chip as it&#39;s reading the data from the last address. (one clock before) I don&#39;t know if the IUL or any other SOPC IP will do this, however.

Here&#39;s a link I found usefull to explain the basics.

http://www.cypress.com/cfuploads/support/a...ntroduction.pdf (http://www.cypress.com/cfuploads/support/app_notes/introduction.pdf)

I think $15 for a 1 MB 32bit memory chip I can read in 6.5ns is pretty good!

Ken