Synchronous SRAM - Instruction and Data memory

Hello,

I think Avalon will present the address/control in one clock. The thing to look at is the timing diagram for the synch ram for an opening access (ie new address). The last parts I used required 3 clocks for an opening access or an address change. After that, an internal address counter takes over, and the device spits out data on every clock. If you move to another non-sequential location, another 3 clocks delay.

Your parts may not work this way.

Eric