Synchronous SRAM - Instruction and Data memory

Eric,

I'm glad you brought this up. There is still time to change if I'm reading the things wrong.

The timing diagrams show that the contents at the address presented on one rising edge are available by the next rising edge. (6.5ns later)

From the perspective of the Nios running off the same 100-133MHz clock how could I do better?

The thing I'm not sure of, and this may be the source of one of your 3 clocks, is whether or not the Nios/Avalon can present the address in 0 clocks or do you essentially spend one clock getting the address setup?

That is if I have 0 setup time in IUL and a LDW is executed, how many clocks until RD# and ADDR are both valid on a rising clock edge?

If its the *next* one for synch vs. *this* one for asynch then that's one clock in asynch's favor.

With Flowthrough I don't see how asynch has an advantage once the address is read in.

Can you explain the source of the three clocks?

Sorry if this is too basic, I&#39;m still learning basics here. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif

Thanks,

Ken