Synchronous SRAM - Instruction and Data memory

Thanks for your comments.

So why do you want to use the synch ram for an implementation that is non-sequential?

I guess cost could be a factor.

An asynch at 10ns could give you 66MHz no wait state bus (rough numbers). Whereas a 133 synch running non sequential

would take 3 clocks per access for 44MHz overall through-put.

Just wondering what your reasons for the synch ram are.

I was considering the latency aware implementation for instruction execution. I am thinking the the UIL glue will still eat up a clock (considering a state machine control circuit). Perhaps some sort of simple logic circuit would preclude loss of clocks. I will have to draw up some bus cycles to see.

Thanks,

Eric