Synchronous SRAM - Instruction and Data memory

I haven't done it yet, but I've got a Synchronous SRAM spec'd into the next spin of my board. After a few days of absorbing details, I decided on Synch SRAM with No Bus Latancy (NoBL also called Zero Bus Turnaround ZBT) with Flow-Through output. (as opposed to pipelined output)

The ZBT is important if you're going to be switching between reading and writing often. (like moving memory within the same module)

The Flow-Through is important as it presents data on every clock as opposed to pipeline that takes two clocks. In reality its almost a wash, because you can clock the pipelined chips almost twice as fast as the Flow-Through.

You can of course make your controller latency aware and even take advantage of the SSRAM's Burst Modes, but in my case, I'm going to be using the ram for table lookups. This means the addresses will be presented in a random order so burst and I think pipelining won't do me any good. (plus I'd rather have a 100-133MHz bus vs. 250MHz bus for the same performance)

FYI, I chose the Cypress CY7C1355B (256K x 36). It can clock upto 133MHz and is available from several sources for $15.

I'm thinking I'll be able to setup fairly aggressive timing using IUL.

Ken