Streaming DMA into NiosI

Ken,

I may be able to help with this problem, as I wrote the DMA controller generator program. Can you clarify this statement:

"The Nios is clocked at 75 MHz, is running in a Cyclone EP1C12, and we are trying to use Dataavailable_n to control the flow for 1-2MHz 32 bit values."

Does this mean that datavalid_n is not synchronized with the 75MHz system clock? If so, I think this is your problem: signals driving the avalon bus really need to be running on the same clock as the rest of the system.

-Aaron