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Honored Contributor
Honored ContributorStrange clock cycle delay in Custom instruction
Hi all!! I implemented a custom instruction with the "Multi-Cycle Custom Instruction" technique. I used: clock, clk_en, reset, start, dataa[31..0], result[31..0]. My custom instruction p...
Altera_ForumHonored Contributor
Honored ContributorHi,
My thought : If you use a multicycle instruction is it at minimum 2 cycles. The first is for setting up the data at your data input ports (from the register file), the second is to wait until it sees the ready signal. I did approximatly the same, and have also a minimum of 2 cycles. STefaan
