Storing states between 2 custom instructions with Nios II processor

One thing to remember is that the custom instruction inputs are (almost) all of the 32 bits of the instruction word, and the two registers values corresponding to the rA and rB fields. What you actually use them for is up to you.

I've not actually determined whether the readra and readrb make any difference, my suspicion is that the logic to suppress the pipeline stall (when they are not asserted) would be too complex. For all other instructions (except call/jmp) only the two lsb bits of the opcode have to be inspected (NFI why it isn't just 1 bit!).