SRAM vs SDRAM

Hi Michael,

> What is the difference in prize of this memory compared to sdram ? half ? twice ?

Depending on density, roughly twice. E.g. for low quantity:

MT48LC8M16 (8M x 16): ~ 10 USD

MT45W8MW16 (8M x 16): ~ 16 USD

MT45W4MW16 (4M x 16): ~ 11 USD

Your mileage may vary ;-)

Regards,

--Scott

Hi smcnutt,

do you use a 16 bit or 32 bit external databus to the psram ??

thanks for your replay nepomuk

> do you use a 16 bit or 32 bit external databus to the psram ??

16-bit

--Scott

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originally posted by smcnutt@Jan 20 2005, 01:29 PM

hi cetic,

> ... i have read in some threads around here that sdram performances

> were quite bad.

i've found the sdram controller performance to be pretty awful. given

the logic area it occupies and its performance, i no longer consider it a

viable alternative for many new designs.

> sram is a bit expensive if i want to have enough memory to run

> my linux (i guess i need at least 4mb).

i've switched to psram (pseudo sram) for new designs. it eliminates

the sdram controller and it performs better[/b]. The cost is

very attractive ... the expense is the number of pins you must use.

Regards,

--Scott

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[/b]

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Scott,

I&#39;ve been consdering using PSRAM for our upcoming NIOS II system, mainly due to it&#39;s much lower power consumption vs DDR.

Do you use the PSRAM as a simple SRAM replacement (in which mode it has quite slow 70ns access times) or do you make use of the Burst mode to get much faster average access rates?

I&#39;ve been tinking about knocking up an interface block to access it in burst mode but the effectiveness of that depends on whether the NIOS can cache grabs it&#39;s instruction stream in bursts or not.

Mark.

Hi Mark,

> Do you use the PSRAM as a simple SRAM replacement (in which mode it has

> quite slow 70ns access times) or do you make use of the Burst mode to get much

> faster average access rates?

I use it as a simple SRAM replacement. As for the access times ... on the board I was

referring to, I was (continue) to use a 50 MHz clock. So compared to SDRAM with

anything more than 3.5 clocks per access, the PSRAM isn&#39;t slow ;-). And I observed

SDRAM performance that was _much_ worse than that. Aside from the extra pins,

the PSRAM was ideal for the application -- and I was able to move to a lower

density FPGA.

Also, to be fair, I haven&#39;t re-visited the matter -- so I don&#39;t know if the SDRAM

controller has improved.

>I&#39;ve been tinking about knocking up an interface block to access it in burst mode

Same here ... I&#39;m thinking the same for our new board. But unfortunately, like many

other things ... it&#39;s still just thinking. ;-) This might be a good candidate to add to

a wish list for the Altera design teams.

Regards,

--Scott

What kind of power restrictions are you on? I persoally don&#39;t think DDR is too heavy on power... that is, without using Vtt termination. I doubt you could get to speeds high enough to require Vtt termination, unless you had multiple chips banked.

Maybe DDR2?

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originally posted by jdhar@Feb 20 2006, 12:11 PM

what kind of power restrictions are you on? i persoally don&#39;t think ddr is too heavy on power... that is, without using vtt termination. i doubt you could get to speeds high enough to require vtt termination, unless you had multiple chips banked.

maybe ddr2?

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Thanks Scott, I agree, a PSRAM IP block from Altera would be very nice!

jdhar: I have looked at DDR and DDR2, though I can only go on what the data sheets tell me as I&#39;ve no personal experience. In our battery powered app a 256Mb DDR looks like taking anywhere between 300mW and 600mW, whereas the equivalent amount of PSRAM takes no more than 120mW.

I don&#39;t really need the full DDR speed, I just want to be able to run one or several NIOS processors at around 80MHz without incurring too much slow down due to slow RAM. PSRAM in burst mode looks like it could be a perfect match, but I&#39;m still in two minds.