SRAM Read/Write too slow

In particular you need to compile everything with -O2 or -O3.

IMHO this should be the default, and you need your head examined before doing anything else.

The Avalon bus write will be at least 2 clocks, they are always synchronous, never 'posted' by the nios (they may be posted by the slave).

Reads are also synchronous, they are also subject to a 2 clock delay before the value can be used (this is after the Avalon cycle completes).

Also check that no 'clock crossing bridges' have been added by the sopc builder - this is rather hard since it won't tell you where it has put them!