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Honored Contributor
Honored ContributorSRAM Problem in Stratix
We have a NIOS design running at a clock speed of 92 MHz in a Stratix part that will have Flash and SRAM. All of our program memory is to reside in SRAM(IDT714V416L) after boot from flash. We ...
Altera_ForumHonored Contributor
Honored ContributorTry to slowdown your clock, the sram on the dev. board is 10ns speed grade, I mean, the tRC and tWC of the SRAM is 10ns. Your system runs at 92M which approaches the upper limit.
