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Altera_Forum
Honored Contributor
12 years agoSPI slave code
Hi, I'm using the QSYS SPI module as a slave. The SPI slave is supposed to receive sequences of bytes/characters. In order to make this happen, I'm using some SW code that reads the stat...
Altera_Forum
Honored Contributor
12 years agoYes, I want to read the data before the next byte arrives, what should the NiosII SW code look like?
I'm now able to receive and collect bytes when the SPI master is sending a single byte at a time. This makes sense from reading: "After a word is received by the slave, the master must de-assert the ss_n signal and reasserts the signal again when the next word is ready to be sent." (I'm assuming a "word" means a byte (8 bits) in my case). I guess the SPI master only asserted the ss_n once when sending a sequence of bytes/characters, but I'll check this using SignalTap. The problem I'm facing now is that the bytes being received on the SPI slave side have a tendency to alternate, I can observe this when the SPI master sends the same byte 4-5 times in a row. Also, from reading the status register, the receive overrun (ROE) bit is not being asserted.