Honored ContributorHi,
i have a bunch of different spi slaves on my bus. Each of these have a different set of likings. I have yet to find any way to control the following at run time: -- Shift direction -- Data polarity and so on. Any of you guys know if this is possible, or is it hardcoded when the cpu is generated? Thanks, Agdepus
Honored ContributorIn the standard SPI peripheral supplied by Altera, the shift direction and clock polarity/phase are fixed when you run SOPC builder. You would need a different SPI peripheral to do what you are looking for.
--- Quote Start --- originally posted by agdepus@Nov 12 2006, 03:34 PM hi,i have a bunch of different spi slaves on my bus.
each of these have a different set of likings.
i have yet to find any way to control the following at run time:
-- shift direction
-- data polarity
and so on.
any of you guys know if this is possible, or is it hardcoded when the cpu is generated?
thanks,
agdepus
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Honored ContributorThanks,
was afraid of that. agdepus http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gifHonored Contributorwas afraid of that.
agdepus http://forum.niosforum.com/work2/style_emoticons/<#emo_dir#>/smile.gif
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--- Quote End --- Hi, You might have a look to the openCores SPI projet. It should do the job. http://www.opencores.org/projects.cgi/web/spi/overview (http://www.opencores.org/projects.cgi/web/spi/overview) The core is Wishbone bus interface based but making it Avalon interface based should not be very difficult. Kind regards.
