SOPC builder

I have the same problem with QII 5.1 SP2.01

I try to create a new component in SOPC Builder (open cores uart16550)

I put all verilog files in a directory under the quartus project directory

/src/uart16550

raminfr.v

timescale.v

uart_debug_if.v

uart_defines.v

uart_receiver.v

uart_regs.v

uart_rfifo.v

uart_sync_flops.v

uart_tfifo.v

uart_top.v

uart_transmitter.v

uart_wb.v

I start component editor and add all the above hdl files, it starts green blinking,

2 files are ok then error occures

Error: command "quartus_map --generate_hdl_interface=C:/work/pro/8dio010_server/8DIO010_FPGA/ce_temp_directory/uart_debug_if.v ce_temp_directory/ce_temp_quartus_project" returned 3

Error (10054): Verilog HDL Compiler Directive error at uart_debug_if.v(90): can't open Verilog Design File "uart_defines.v" File: C:/work/pro/8dio010_server/8DIO010_FPGA/ce_temp_directory/uart_debug_if.v Line: 90

Error (10112): Ignored module "uart_debug_if" at uart_debug_if.v(92) due to previous errors File: C:/work/pro/8dio010_server/8DIO010_FPGA/ce_temp_directory/uart_debug_if.v Line: 92

Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 2 warnings

Error: Processing ended: Tue Jul 25 20:03:15 2006

Error: Elapsed time: 00:00:01

Error: C:/work/pro/8dio010_server/8DIO010_FPGA/ce_temp_directory/uart_debug_if.v.xml does not exist

after all errors I cannot select uart_top as top level module

can someone please help me because I only know vhdl and not much verilog,

has anybody already created this uart in sopc builder ?

thanks