SOPC builder reports "Generating non-optimal logic"

Datasheet "Using Tightly Coupled Memory with the Nios II Processor", April 2009, p.11:

"To simplify address decoding, you can map the high-order address

bit to a unique location. By limiting the decoding logic to one bit, you

minimize the effect of address decoding on fMAX. The Nios II

component works correctly even if the address map is not optimal;

however, it displays a warning during system generation.

As an example of optimal address mapping, if all the normal

memories and peripherals in your system occupy addresses below

0x2000000, mapping your tightly coupled memories at addresses

from 0x2000000 and above satisfies this requirement."