SOPC Builder clock domain crossing

The design is for an Cyclone 1C12.

Besides the NIOS II core three other masters can access the Avalon Bus, which drives two banks of SRAM, a Flash memory and several other peripherals (PIOs, slave interfaces to user logic).

The system divides into a pure NIOS part, which owns one of the SRAM banks and the flash, and a hardware reading data from the other SRAM bank. These data have been written by the NIOS before.

This hardware should be able to run at a faster clock than the NIOS section, therefore using two independent clocks would be nice.

Two different errors occur:

If I change the clock source of only one of the peripherals to the new added clock source, Quartus 4.2 comes up with an error message during synthesis, I guess of the abrbitrator logic of my NIOS system.

Partitioning the whole systems with the different clocks to use causes the SOPC Builder to fail when generating arbitration and system (top) modules.

Here a short copy of the SOPC Builder's output:

Altera SOPC Builder Version 4.20 Build 156

Copyright © 1999-2004 Altera Corporation. All rights reserved.

# 2004.12.12 22:12:35 (*) mk_custom_sdk starting# 2004.12.12 22:12:36 (*) Finding all CPUs# 2004.12.12 22:12:36 (*) Finding all available components# 2004.12.12 22:12:36 (*) Found 46 components

...# 2004.12.12 22:12:39 (*) Starting generation for system: ptu9_nios_release.

..................................................# 2004.12.12 22:12:43 (*) Running Generator Program for ext_flash# 2004.12.12 22:12:45 (*) Running Generator Program for ext_ram# 2004.12.12 22:12:48 (*) Running Generator Program for ext_nios_sram# 2004.12.12 22:12:51 (*) Running Generator Program for onchip_memory_0# 2004.12.12 22:13:38 (*) Running Generator Program for cpu

...

Redirecting generation messages for cpu to file cpu_gen_log_0.txt# 2004.12.12 22:14:31 (*) Running Generator Program for Timer0

...

# 2004.12.12 22:16:16 (*) Making arbitration and system (top) modules.

---wh false:false:boolean

---wh __6__:std_logic'('0'):1

---wh irq_n_from_the_Timer5_from_sa:irq_n_from_the_Timer5_from_sa:1

---wh __8__:std_logic'('0'):1

---wh irq_from_the_pci_user_if_from_sa:irq_from_the_pci_user_if_from_sa:1

---wh irq_n_from_the_Timer6_from_sa:irq_n_from_the_Timer6_from_sa:1

---wh spi_dac_spi_control_port_irq_from_sa:spi_dac_spi_control_port_irq_from_sa:1

---wh irq_n_from_the_ptu_input_pio_from_sa:irq_n_from_the_ptu_input_pio_from_sa:1

---wh __10__:std_logic'('0'):1

---wh __1__:std_logic'('0'):1

---wh low_priority_timer2_s1_irq_from_sa:low_priority_timer2_s1_irq_from_sa:1

---wh jtag_uart_0_avalon_jtag_slave_irq_from_sa:jtag_uart_0_avalon_jtag_slave_irq_from

_sa:1

---wh irq_n_from_the_Timer7_from_sa:irq_n_from_the_Timer7_from_sa:1

---wh irq_n_from_the_Timer0_from_sa:irq_n_from_the_Timer0_from_sa:1

---wh irq_n_from_the_usb_user_if_from_sa:irq_n_from_the_usb_user_if_from_sa:1

---wh __12__:std_logic'('0'):1

---wh __3__:std_logic'('0'):1

---wh __5__:std_logic'('0'):1

---wh irq_n_from_the_Timer8_from_sa:irq_n_from_the_Timer8_from_sa:1

---wh irq_n_from_the_Timer1_from_sa:irq_n_from_the_Timer1_from_sa:1

---wh true:true:boolean

---wh __7__:std_logic'('0'):1

---wh irq_n_from_the_sequencer_if_from_sa:irq_n_from_the_sequencer_if_from_sa:1

---wh irq_n_from_the_Timer2_from_sa:irq_n_from_the_Timer2_from_sa:1

---wh timer1_int_s1_irq_from_sa:timer1_int_s1_irq_from_sa:1

---wh __9__:std_logic'('0'):1

---wh clk_clk_nios_:clk_clk_nios_:1

---wh __0__:std_logic'('0'):1

---wh irq_n_from_the_Timer3_from_sa:irq_n_from_the_Timer3_from_sa:1

---wh __2__:std_logic'('0'):1

---wh __11__:std_logic'('0'):1

---wh irq_n_from_the_Timer4_from_sa:irq_n_from_the_Timer4_from_sa:1

---wh __4__:std_logic'('0'):1

---wh __13__:std_logic'('0'):1

ERROR:

-- ERROR: Order: LEFT VALUE (-1) NOT A NUMBER

-- Expression: {1'b0,

1'b0,

1'b0,

1'b0,

1'b0,

1'b0,

1'b0,

1'b0,

1'b0,

1'b0,

1'b0,

1'b0,

1'b0,

1'b0,

clk_clk_nios_~irq_n_from_the_sequencer_if_from_sa,

clk_clk_nios_~irq_n_from_the_ptu_input_pio_from_sa,

clk_clk_nios_~irq_n_from_the_Timer8_from_sa,

clk_clk_nios_~irq_n_from_the_Timer7_from_sa,

clk_clk_nios_~irq_n_from_the_Timer6_from_sa,

clk_clk_nios_~irq_n_from_the_Timer5_from_sa,

clk_clk_nios_~irq_n_from_the_Timer4_from_sa,

clk_clk_nios_~irq_n_from_the_Timer3_from_sa,

jtag_uart_0_avalon_jtag_slave_irq_from_sa,

~irq_n_from_the_usb_user_if_from_sa,

clk_clk_nios_~irq_n_from_the_Timer2_from_sa,

timer1_int_s1_irq_from_sa,

irq_from_the_pci_user_if_from_sa,

low_priority_timer2_s1_irq_from_sa,

clk_clk_nios_~irq_n_from_the_Timer1_from_sa,

clk_clk_nios_~irq_n_from_the_Timer0_from_sa,

1'b0,

spi_dac_spi_control_port_irq_from_sa}

Error in processing. System NOT successfully generated.

Before jumping the gun: What version of Quartus/SOPC Builder? The final release 4.2 version?? pre-release & beta versions did not support the clock-domain crossing feature as noted in the readmes/release notes.

The final release, which came out of engineering's hands barely a week ago (build 157, I believe), suppors the clock-crossing feature.

By the way this is one of the most powerful performance features to be introduced in some time for our tools. Being able to put custom-logic or a tri-state bridge with many masters (things that slow clock speeds down) onto their own domain lets one easily achieve max performance out of the CPU and other peripherals.

My Quartus (and SOPC Builder) is Version 5.2, Build 156 :-(.

I read nothing about clock domain crossing is an unsupported fetures in the readme file.

Anyway, I downloaded the 4.2 as web edition from the Altera homepage appr. 12|11|2004, but run it as licensed one. May this influence the behaviour?

Sure, I hope the clock domain crossing feature will boost performance, now we're about 88MHz with a Cyclone 1C12C324-7 and expect to get the 100MHz +.

Earlier I thought of braking up my NIOS system into two independent Avalon Busses, a slow one with the NIOS inside and a fast one, just connecting to one SRAM bank and the user logic, but the clock domain crossing feature is exactly what we need.

When you get to use the clock domain crossing make sure that you keep the memory at the same speed as the NIOS core.

I'm guessing you meant Quartus 4.2. The webpack is build 156. Like Jesse said, clock crossing is in build 157 (you are one build too early)

There are two memory banks (SRAM), one is dedicated to NIOS (runs with the NIOS core's clock), the other one is read by user logic at max. speed, the NIOS should be able to write to this memory at reduced speed. So I'd like to run this memory bank (via a tristate bridge) with the same clock as the user logic, which accesses the bank through a master interface to the Avalon Bus.

Do you consider a memory bottle neck, if the memory does not run with the NIOS's clock? The NIOS is an f-core with both 4k instruction and data cache.

Running your memory at the same speed as the processor has it's advantages (look at today's PCs and how the system bus bogs down the entire system). I can't think of the reason why the memory would have to be at the same speed as the NIOS core, but I seem to remember hearing that it does when I learned about the clock crossing for the first time.

James or Jesse should know that one, or maybe I was just hearing things.

Cheers

Hi,

Sorry to write back late. I made an incorrect assumpion about the versions in that I was thinking that (at at the time) it was likely you were using a beta/pre-release not-supporting clock-crossing; build 156 as you have downloaded should include these features.

I spoke with someone familiar with clock-crossing and we think we know the cause & fix to this. Can you please contact Altera applications via phone or mySupport and file a report on the problem, including the ".ptf" file for the system you're building? That way we can confirm the problem and, if possible, post a workaround here on the forum for others' benefit as well.