SOPC Builder clock domain crossing

There are two memory banks (SRAM), one is dedicated to NIOS (runs with the NIOS core's clock), the other one is read by user logic at max. speed, the NIOS should be able to write to this memory at reduced speed. So I'd like to run this memory bank (via a tristate bridge) with the same clock as the user logic, which accesses the bank through a master interface to the Avalon Bus.