SOPC Avalon Timing

hello quan1328

first it depends if it's an external component.

if yes, then you must have a look into the datasheet and timing

for this component.

if it is an internal component, then you determine the timing with your

vhdl or verilog code.

for internal components, i use the waitrequest avalon signal to handle

the timing. then you don't have to enter the avalon timing values.

e.g. reading a register from an internal component requires e.g. 1 clock cycle,

while reading from a fifo or other ram component normally needs 2 or 3

clock cycles.

see 3.2.2 Slave Read Transfer, Wait states

http://altera.com/literature/manual/mnl_avalon_spec.pdf (http://altera.com/literature/manual/mnl_avalon_spec.pdf)