SOPC and async sram how ?

I'll try to answer the second one since I've never swam the asyn ram waters.

Depending on how you want to implement your system, different designs with the NIOS II processor are possible. If you are offloading DSP type calculations then I recommend using custom instructions with registers that you can configure. So you would pre-configure these registers then start using the hardware as a whole as custom instructions. If you are simply programming a filter that is implemented in DSP hardware then I would create external hardware that programs the DSP multipliers on the fly.

As you can see I'm staying general to avoid a lot of typing before I know more about the system. Could you explain what the NIOS is doing, is it just reading the output from a filter (so data feed directly into the filter), what data rate you need, etc.....

Hello BadOmen.

Thanks for answering. The Filterorders and coefficents are calculated by matlab. I will upload these datas

via my host pc software to the nios cpu. The nios should than disable or enable some of the TAP's or biquad

sections to get the right filterorder. The filters should be on the fpga. For the coefficents i have thought about an lookup table feed by the nios cpu but i have no idea on how to do this http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/huh.gif

The filter should work on 100Mhz if possible. The AD converter is connected to the cyclone.

I&#39;m a newbee and i have no idea on how to begin so any

guidelines or code segments to get an introduction are welcome.

What should i do first ?

Thanks

Andreas

If you stick with FIR filters, the solution which is most straightforward is to use the altera FIR compiler. Generate a filter with reloadable coefficients and you&#39;l get a port through which you can load coefficients in a serial manner (one coefficient at a time) This hooks to avalon very easily with a PIO if you dont have time critical reload constraints. Otherwise you could use the arlut_fifo_interface to connect to the port, and you will be able to write directly to the port without handshaking your way through loading. arlut_fifo_interface is published here on nios forum. Filters with more than 100 taps and 100MHz is posible. If you want lower order, simply load excess coeffients to 0, or build a new block with fir compiler. During reload you will have to discard data comming from the filter.

With fir compiler you can play with different filter structures to get a good match between resources and performance. One issue important for resource usage is the clock latency. One sample per clock would require the most logic cells.

I have not used altera IIR compiler, so dont know about reload there.

Async ram with nios: I would guess its as simple as adding one of the standard extern ram blocks in sopc builder. They are async ones, used in most of the kits. If not, use a avalon tristate bridge.

Ok, so you want to control the filter instead of making a DSP processor using the NIOS II core. In this case I would next determine the hardware structure of the filter. Getting the numbers from the NIOS to the hardware will not be difficult so I think the actual DSP portion of the project will be the challenge (not sure that will make things easier or harder for you).

The lookup table aspect has me a bit confused since I would just program registers that feed the multipliers (just send the coefficients to the NIOS processor and have it program your filter using the "Interface to User Logic (IUL)" in SOPC builder) but perhaps you have some size constraints that need to be taken into consideration. I also noticed that you are using a Cyclone FPGA, are you aware that it does not have dedicated DSP hardware? So every multiplier or MAC you have in your design is going to require quite a few resources. So to answer your question of where to start I think the filter itself would be the first step. In Matlab filters cranked out with 50 coefficients are nice, but if you try to implement a true FIR chain of these in an FPGA you will run out of room fast. Instead I would determine the sampling rates and the computational times you need and try to share logic resources.

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Are your samples coming in at high rates? If that&#39;s the case then not only do you need a true FIR chain, but you may need a Stratix device (hardware multiplies). In short if you get the filter into the design, then the rest will be easy.

Forgot about DSP builder (duh). It&#39;s your best bet in this case and compilments SOPC builder very well.

But again, consider the filter first before determining how to connect it to an SOPC system. And for IIR good luck because that&#39;s a tricky beast to implement in general.