SOPC - No Nios + SDRAM = Problem

Hello all,

Does anyone have any experience with instantiating the Switched Fabric (SOPC) without Nios CPUs? I'm having an issue doing so with SDRAM. Any pointers are appreciated

I've written my own simple avalon "External Master Bus" which simply brings the write_data/write/read_data/read/bus_busy signals outside the switched fabric block and connected to my own MCU EMIF host. I can read and write to the switched fabric PIO's and on chip memories no problem but cannot access the SDRAM.

I'm using a 'SDRAM Controller' to connect to a Stratix II development board's U57 SDRAM device. Writes appear to take a single clock cycle (50 MHz) and reads take 10 clock cycles (how long bus-busy is held for + 1 issuing cycle). However, all reads always return 0xFF. I've pritty much copied the SDRAM setup (PLL, etc) from an Altera example.

My master data width is 16 bits, but as the onchip memory is 32 bits and works (the SDRAM is also 32 bits). So I do not think it could be an addressing problem. (besides, the SDRAM is dynamic memory addressing anyways).

Note: This SDRAM works fine under the examples provided by Altera.

Can anyone suggest anything I should look at? I'm a little stumped right now.

Thanks a bunch,

Kevin