Honored Contributor
Honored Contributor
i am a new nios ii user and my environment is quartus 5.0(win)+sopc builder 5.0. the thing i want to do is to build a custom component in vhdl which could be used to communicate with the avalon bus.
first, i have reviewed the pwm given by offical alera website which is written in verlig. as i have seen from this example, the design is implemented in three files, including one top level file, one register description file and one custom logic file.
so my question is does the registers description file necessary for all compeonent?? in another word, let's say how does sopc builder know and assign spaces to different register, and also in which order is the space assigned according the vhdl file as i know that the device driver in software seems can be neglected in here.
another question is i have tried to make my design work regardless with the up question, which seems to be ok to run, but only run by modelsim. when i use the instruction set simulator to run program and try to read data from the registers, all they become zero. but in modlesim i can see clearly the correct data has been put on avalon_readdata signal within the read phase. why can not get in my program?? why why why?? http://forum.niosforum.com/work2/style_emoticons/<#emo_dir#>/mad.gif http://forum.niosforum.com/work2/style_emoticons/<#emo_dir#>/mad.gif http://forum.niosforum.com/work2/style_emoticons/<#emo_dir#>/mad.gif
i'm a new user of alera nios, so plz give me some help
any kind of discussion will be welcomed
thx a lot
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--- Quote End --- You can partition your component into as many source files as you like. The separation to interface, registers and logic is for convinience only. Note, however, that whenever you change your top file, you will have to assign the Avalon bus port role in the component editor all over again. Avishay.
