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Altera_Forum
Honored Contributor
Honored ContributorSoftware runs w/o reloading on changed FPGA design
Help me understand following observation: 1. I have created FPGA design with Signal Tap, NIOS II cpu, 4k of internal RAM, EPCS flash. 2. I have created a piece of software linked to be cop...
Altera_ForumHonored Contributor
Honored ContributorBug.
At least if things should have changed it's a bug. I haven't worke don Signal Tap for 3-4 years, so it's hard for me to remember. Plus it's been re-written.
