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Altera_Forum
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21 years ago

Software runs w/o reloading on changed FPGA design

Help me understand following observation: 1. I have created FPGA design with Signal Tap, NIOS II cpu, 4k of internal RAM, EPCS flash. 2. I have created a piece of software linked to be cop...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

Bug.

At least if things should have changed it's a bug.

I haven't worke don Signal Tap for 3-4 years, so it's hard for me to remember. Plus it's been re-written.