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Altera_Forum
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21 years ago

Software runs w/o reloading on changed FPGA design

Help me understand following observation: 1. I have created FPGA design with Signal Tap, NIOS II cpu, 4k of internal RAM, EPCS flash. 2. I have created a piece of software linked to be cop...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

I **think** (I could be wrong) that it is because when it is running fast, it is running out of flash. WHen you download a design, that design starts running (not the one in flash). When you powercycle the board, it starts out of flash again.