ryangjoraasNew Contributor1 year agoSimulating Nios V/g error (cannot compile encrypted .sv file) I generated the HDL and the testbench files successfully from Platform Designer for my Nios V/g .qsys system. I am now trying to simulate now in Aldec Riviera-Pro but I am getting the error message...Show More
Recent DiscussionsError generating BSPSolvedNIOS V/m dbg_reset_out signal (Q25.1 Std, MAX10)SolvedWhere is FreeRTOS-Plus-TCP DesignSolvedNIOS-V QSYS Warning Properties (associatedClock) have been set onSolvedDK-DEV-AGI027-RA: JTAG chain broken after Nios V Hello, FPGA recovery fails