Forum Discussion
Altera_Forum
Honored Contributor
15 years agook I think I have fixed the problem runing from the console:
perl c:/altera/10.1/quartus/sopc_builder/bin/run_modelsim.pl c:/altera/10.1/modelsim_ase/win32aloem,c:/Users/ifdm/workspace/quartus/ifdm_project,mvbc_system But my problem now is that in the simulation I don`t see any changes in the instruction buses of the cpu. Neither see any data in the jtag_uart_log. The ram is initalized with the code of the program with elf2hex, elf2dat and nios2_elf_nm because I have introduced this line NIOS2_BSP_ARGS="--default_sections_mapping sdram" in create-this-bsp file. My simulation lasts 1 ms, 1000 us , maybe is a short time. I am thinking of using these simulation options: small c library and reduced device drivers. Any idea in how to take less time in simulation and how to fix the problem no-instruction-interaction with the cpu in the program simulation?