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Altera_Forum's avatar
Altera_Forum
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15 years ago

signed division

Hi all, I design a piece of hardware using simple division as shown in below: module divider (in1, in2, division, multiply); //parameter parameter DATA_WIDTH = 32; //Input in...
Altera_Forum's avatar
Altera_Forum
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15 years ago

I can't see a signed type definition in your code. By Verilog specification, you're performing unsigned arithmetic, which would pretty explain the issue.