set_output_delay explained for dummies

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#        launch edge                     
#                   |                               
#                   |                               
#                   V                               
#                    ________________                ________________
#  Launch CLK ______|                |______________|                |_____________
#                   ^                               ^
#                   t=0.0                           t=10.0
#  
#                     _______________
#  Data       XXXXXXXX___V_A_L_I_D___XXXXXXXXXXXXXXXX  
#                     ^             ^
#                     t=1.0         t=3.0
# 
#                                          latch edge
#                                                   |
#                                                   |
#                                                   V
#                    ________________                ________________
#  Latch Clk _______|                |______________|                |_____________
#                   ^                               ^
#                   t=-10.0                         t=0.0
#                                                   ^
#                     _______________               |
#  Data       XXXXXXXX___V_A_L_I_D___XXXXXXXXXXXXXXX|
#                     ^             ^               |
#                     t=-9.0        t=-7.0          |
#                                                   |
#                     <--------max(+)---------------|
#                                    <----min(+)----|
# 
#     max/min arrows point to positive value convention
# 
#     set_output_delay -max 9
#     set_output_delay -min 7
# 
# 
# 
#  Alternative
# 
#        launched here                        latched here
#                   |                               |
#                   |                               |
#                   V                               V
#                    ________________                ________________
#  Latch Clk _______|                |______________|                |_____________
#                   ^                               ^
#                   t=-10.0                         t=0.0
#                                                   ^
#                                                   |   _______________
#  Data       XXXXXXXX??????????xxxxxxxxxxxxxxxxxxxx|xxx___V_A_L_I_D___xxxxxxxxxx
#                                                   |   ^             ^
#                                                   |   t=1.0         t=3.0
#                                                   |
#                                                   |---> max(-)
#                                                   |-----min(-)------>
# 
#     set_output_delay -max -1
#     set_output_delay -min -3

I'm not sure I get the difference between method 1 and method 2. They are essentially defining the same setup and hold times, just at different points. Would the 2nd version indicate that when I launch the output data, it would take an extra clock cycle before being latched compared with 1st version?