Honored Contributor
Honored Contributor@Cris72: Thanks for the reply. I don't know how to place appropriate timing constraints on the Nios SOPC system, since I didn't design the IP cores used there. I would have expected that any needed timing constraints would have been generated automatically together with the modules generated by SOPC Builder. Possibly if I had source code for the UART core IP, I could improve on the timing constraints, or otherwise debug the IP, but I don't know if that's available. As it is, I didn't notice any timing errors during the Quartus workflow.
The problem with trying to debug the assembler code is knowing where to focus attention - the crashes seem to be happening nondeterministically, at seemingly random time points; and when the crash happens, I might find myself in an endless loop, or back in the system initialization code, but I don't know how/why I got there. And when single-stepping, the behavior is different yet again, because the external systems that are generating our serial input asynchronously aren't being paused by the Nios debugger. So stepping through the code ends up not being very helpful. I don't think it's a stack problem... My code isn't recursive and has only a few levels of functions. But I'll try cutting down on the local variables and see if that helps...
