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1) Is it possible that changes to the outside design could shift placement/routing in ways that cause subtle timing glitches within the Avalon UART core IP to manifest themselves?
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Yes, it is possible.
Is your design correctly timing constrained? And does it meet timing after compilation?
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2) How does one usually debug or workaround these kinds of problems? It's very frustrating, because the code crashes in a different place each time, and I can't even step into the point where it's crashing with the source-level debugger. I don't have source code for the system runtime or the megafunction IP.
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I think you should be able to step into the read(),fgets()... functions at the assembler level, even if you don't have source code, in order to identify the exact point where your code hangs.
Maybe you can not debug into those functions just because the hang/restart behavior happens exactly when you call the function. Then you possibly have a system stack overflow. Do you use big local variables or recursive functions?
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