Forum Discussion
Altera_Forum
Honored Contributor
12 years agoSerial communication and interval timer integration problems
I'm required to build a Nios based fpga firmware for a specific system, which includes UART RS-232 communication. The communication itself based on packets of 20 bytes, with time outs between bytes r...
Altera_Forum
Honored Contributor
12 years agoYou have 50000 clocks there.
What you can't see is the delay between the timer hitting its count and the cpu performing the first IORD/IOWR. It is likely to be the same for every expiry - so everything will look fine - until your ISR processing takes all the cpu time. IORD/IOWR themselves are likely to be 3 clocks (plus time to get the data to write, and fetch any code from external memory if you aren't executing from tightly coupled instruction memory and the code isn't still in the cache), but the time to save the registers and then call your ISR is a lot.